Computer Architecture Basics
The course teaches fundamental computer architecture concepts, covering number systems, CPU design, memory hierarchy, instruction sets, and I/O, enabling students to grasp how hardware and software interact.
Who Should Take This
Undergraduate engineering majors, aspiring system designers, and tech‑savvy hobbyists with basic programming experience should enroll. They seek a solid conceptual foundation in hardware organization, aiming to interpret performance trade‑offs, read assembly code, and collaborate effectively with hardware teams in their future careers.
What's Included in AccelaStudy® AI
Adaptive Knowledge Graph
Practice Questions
Lesson Modules
Console Simulator Labs
Exam Tips & Strategy
20 Activity Formats
Course Outline
66 learning goals
1
Number Systems & Data Representation
4 topics
Number Bases and Conversions
- Identify and describe the positional notation used in binary, octal, decimal, and hexadecimal number systems
- Convert integers and fractions between binary, octal, decimal, and hexadecimal representations using repeated division and multiplication methods
- Perform binary addition, subtraction, multiplication, and division and verify results by converting to decimal
Integer Representation
- Describe unsigned, sign-magnitude, one's complement, and two's complement integer encoding schemes and state the range of each for a given bit width
- Apply two's complement arithmetic to add and subtract signed integers and detect overflow conditions
- Analyze why two's complement is preferred over sign-magnitude in modern hardware by comparing circuit complexity and edge-case behavior
Floating-Point and Character Encoding
- Describe the IEEE 754 single-precision and double-precision floating-point formats including sign, exponent, and mantissa fields
- Convert decimal numbers to IEEE 754 binary representation and identify special values such as infinity, NaN, and denormalized numbers
- Analyze precision limitations and rounding errors in floating-point arithmetic and explain why certain decimal values cannot be represented exactly
- Identify ASCII, Unicode, and UTF-8 character encoding schemes and describe how multi-byte encodings represent international character sets
Boolean Algebra and Logic Gates
- List the fundamental logic gates (AND, OR, NOT, NAND, NOR, XOR, XNOR) and construct truth tables for each
- Apply Boolean algebra laws (De Morgan's, distributive, associative) to simplify combinational logic expressions
- Evaluate how multiplexers, decoders, and adder circuits are constructed from basic logic gates to perform data selection and arithmetic
2
CPU Architecture
4 topics
Datapath and Control Unit
- Identify the major components of a CPU datapath including the ALU, register file, program counter, and instruction register
- Trace the flow of data through the datapath during fetch, decode, execute, memory access, and write-back stages for a sample instruction
- Compare hardwired control versus microprogrammed control and evaluate the trade-offs in design complexity, speed, and flexibility
Registers and ALU Operations
- Describe the purpose of general-purpose registers, special-purpose registers (PC, SP, flags), and the role of the register file in instruction execution
- Apply register transfer notation to describe how arithmetic, logic, and shift operations execute within the ALU
- Analyze how condition flags (zero, carry, overflow, negative) are set by ALU operations and used by conditional branch instructions
Clock and Instruction Execution
- Describe the role of the system clock in synchronizing CPU operations and define clock cycle, clock rate, and clock period
- Calculate execution time for a sequence of instructions given CPI values, clock rate, and instruction count using the CPU performance equation
- Evaluate how instruction mix and CPI variations across instruction types affect overall processor performance
Multi-Core and Parallel Architectures
- Describe the motivation for multi-core processors and explain why power consumption limits prevented continued single-core clock frequency scaling
- Classify Flynn's taxonomy of computer architectures (SISD, SIMD, MISD, MIMD) and identify which category common processor designs belong to
- Analyze cache coherence challenges in multi-core systems and describe how snooping and directory-based protocols maintain data consistency
3
Memory Hierarchy
3 topics
Cache Memory
- Describe the principles of temporal and spatial locality and explain why cache memory exploits these access patterns to reduce average memory access time
- Compare direct-mapped, fully associative, and set-associative cache organizations in terms of hit rate, hardware cost, and access latency
- Calculate cache hit rates, miss penalties, and average memory access time for given cache configurations and access patterns
- Describe write-through, write-back, and write-allocate cache policies and state the trade-offs in consistency versus performance
Main Memory and RAM
- Identify the differences between SRAM and DRAM in terms of storage cell structure, speed, density, cost, and typical use cases
- Explain how DRAM refresh cycles work and describe the impact of refresh overhead on effective memory bandwidth
- Analyze the memory hierarchy from registers through L1, L2, L3 cache to main memory and evaluate the cost-performance trade-offs at each level
Virtual Memory
- Describe the concept of virtual memory and explain how it provides process isolation and the illusion of a large contiguous address space
- Apply page table lookups to translate virtual addresses to physical addresses and calculate the effect of page size on table size and fragmentation
- Evaluate the role of the TLB in accelerating address translation and analyze the performance impact of TLB misses on memory-intensive workloads
- Compare page replacement algorithms (LRU, FIFO, clock) and evaluate their effectiveness in reducing page fault rates for different access patterns
4
Instruction Sets & Assembly Concepts
4 topics
ISA Design Principles
- Define what an instruction set architecture is and list the key design decisions including opcode encoding, operand count, and data types
- Compare RISC and CISC instruction set philosophies and evaluate their impact on pipeline design, code density, and compiler complexity
- Classify instruction types (arithmetic, logic, data transfer, control flow) and describe the role of each category in program execution
Addressing Modes
- List and describe common addressing modes including immediate, register, direct, indirect, indexed, and base-plus-offset
- Apply different addressing modes to access array elements, struct fields, and stack frames in assembly-level code examples
- Evaluate the trade-offs between addressing mode flexibility and instruction encoding complexity in fixed-length versus variable-length ISAs
Assembly Language Concepts
- Describe the relationship between assembly language mnemonics, machine code, and the assembler translation process
- Implement simple programs using assembly-level pseudocode including loops, conditionals, and function calls with stack management
- Analyze how high-level language constructs (if-else, for loops, function calls) are compiled into assembly instruction sequences
Instruction Encoding and Formats
- Identify R-type, I-type, and J-type instruction formats and describe the fields (opcode, rs, rt, rd, immediate, address) in each
- Encode and decode sample instructions by mapping assembly mnemonics to their binary machine code representations using an instruction format table
5
I/O Systems
4 topics
Buses and Interfaces
- Describe the role of system buses (data, address, control) in connecting CPU, memory, and I/O devices
- Compare serial and parallel bus architectures and evaluate bandwidth, latency, and scalability trade-offs for modern I/O interconnects
I/O Techniques
- Describe programmed I/O, interrupt-driven I/O, and direct memory access (DMA) and state when each technique is appropriate
- Apply interrupt priority schemes to determine the order in which multiple pending interrupts are serviced by the CPU
- Evaluate how DMA controllers reduce CPU overhead during bulk data transfers and analyze the impact on bus contention
Storage Interfaces
- Identify common storage interfaces (SATA, NVMe, USB) and describe the bandwidth and latency characteristics of HDD versus SSD storage
- Compare the access patterns and performance profiles of magnetic disk, NAND flash, and emerging non-volatile memory technologies
- Analyze how the storage hierarchy (registers, cache, RAM, SSD, HDD) balances cost per bit against access latency and evaluate Amdahl's storage axiom
I/O Performance and Interfacing
- Describe memory-mapped I/O versus port-mapped I/O and explain how each approach maps device registers into the processor's address space
- Calculate effective I/O bandwidth given bus width, clock frequency, and transfer protocol overhead for common interconnect standards
6
Pipelining & Performance
3 topics
Pipeline Fundamentals
- Describe the five classic pipeline stages (IF, ID, EX, MEM, WB) and explain how instruction-level parallelism increases throughput
- Calculate the ideal speedup of a pipelined processor and determine the actual throughput given pipeline stage latencies and stall cycles
Pipeline Hazards
- Identify structural, data, and control hazards in a pipelined processor and describe the conditions under which each type occurs
- Apply forwarding (bypassing) and stalling techniques to resolve data hazards in a five-stage pipeline execution trace
- Evaluate branch prediction strategies (static, dynamic, branch target buffer) and analyze their effectiveness in reducing control hazard penalties
Performance Metrics and Optimization
- Define throughput, latency, CPI, MIPS, and FLOPS as processor performance metrics and state the limitations of each as a single benchmark
- Apply Amdahl's law to calculate the maximum speedup achievable by parallelizing a fraction of a program's execution
- Analyze the diminishing returns of increasing parallelism using Amdahl's law and evaluate when architectural improvements yield meaningful performance gains
- Compare single-core performance optimization techniques (deeper pipelines, superscalar execution) with multi-core parallelism approaches
Hands-On Labs
15 labs
~380 min total
Console Simulator
Code Sandbox
Practice in a simulated cloud console or Python code sandbox — no account needed. Each lab runs entirely in your browser.
Scope
Included Topics
- Number systems (binary, octal, hexadecimal) and conversions, integer and floating-point representation, character encoding, Boolean algebra and logic gates, CPU datapath and control unit design, registers and ALU operations, clock cycles and instruction execution, cache memory hierarchy (L1/L2/L3), virtual memory and paging, RAM types (SRAM/DRAM), RISC vs CISC instruction set architectures, addressing modes, assembly language concepts, instruction encoding and formats, I/O interfaces and buses, interrupts and DMA, pipelining stages and hazards, performance metrics (CPI, throughput, speedup), Amdahl's law and parallelism fundamentals
Not Covered
- FPGA and VLSI circuit design
- Specific ISA deep-dives (x86 microcode, ARM Thumb encoding details)
- Operating system internals beyond memory management basics
- Quantum computing architectures
- GPU architecture and GPGPU programming
- Network-on-chip and advanced interconnects
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